With integration density of semiconductor devices becoming higher and the semiconductor devices becoming smaller, a multi-layered line (wiring) structure is employed in semiconductor device fabrication. With the multi-layered line structure, formation of via holes and metal lines in turn becomes an important factor in semiconductor device fabrication.
FIG. 1 illustrates a section of a metal line layer in a related high voltage semiconductor device. As shown in FIG. 1, the metal line layer includes a lower metal line 115 formed over a semiconductor substrate 110, an interlayer insulating film 120 exposing a portion of the lower metal line 115, a barrier layer 125 formed over the lower metal line 115 exposed thus, and an upper metal line 130 formed over the barrier layer 125.
During wire bonding on the upper metal line 130, physical damage can occur under the metal line layer in a device formed at an active region of the semiconductor substrate 110. In general, the thickness of AlCu used as the lower metal line is as thin as 4000 Å. An impact generated during wire bonding is directly transmitted to the device formed at the active region of the semiconductor substrate 110, to cause the damage.